L. Benini and G. D. Micheli, Networks on chips: a new SoC paradigm, IEEE Computer, 2002.

A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg et al., Network on chip: An architecture for billion transistor era, Proc. of the International NorChip Conference, 2000.

P. Guerrier and A. Greiner, A generic architecture for onchip packet-switched interconnections, Proc. Design and Test in Europe (DATE), pp.250-256, 2000.
URL : https://hal.archives-ouvertes.fr/hal-01573605

S. K. , A network on chip architecture and design methodology, Proc. IEEE Computer Society Annual Symp. on VLSI, pp.117-124, 2002.

W. J. Dally and B. Towles, Route packets, not wires: Onchip interconnection networks, Proc. Design Automation Conf. (DAC), pp.683-689, 2001.

F. Karim, An interconnect architecture for networking systems on chips, IEEE Micro, vol.22, issue.5, pp.36-45, 2002.

P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, Design of a switch for network on chip applications, Proc. Int. Symp. Circuits and Systems (ISCAS), vol.5, pp.217-220, 2003.

P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, Performance evaluation and design trade-offs for networkon-chip interconnect architectures, IEEE Trans. Comput, vol.54, issue.8, pp.1025-1040, 2005.

C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete et al., Dynoc: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conf. on FPL, 2005.

M. Majer, C. Bobda, A. Ahmadinia, and J. Teich, Packet routing in dynamically changing networks on chip, Proc. of 19th IEEE International Parallel and Distributed Symposium, 2005.

C. Bobda and A. Ahmadinia, Dynamic interconnection of reconfigurable modules on reconfigurable devices, Design & Test of Computers, vol.22, pp.443-451, 2005.