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Ultra-High Performance and Low-Cost Architecture of Discrete Wavelet Transforms

Abstract : This work targets the challenging issue to produce high throughput and low-cost configurable architecture of Discrete wavelet transforms (DWT). More specifically, it proposes a new hardware architecture of the first and second generation of DWT using a modified multi-resolution tree. This approach is based on serializations and interleaving of data between different stages. The designed architecture is massively parallelized and sharing hardware between low-pass and high-pass filters in the wavelet transformation algorithm. Consequently, to process data in high speed and decrease hardware usage. The different steps of the post/pre-synthesis configurable algorithm are detailed in this paper. A modulization in VHDL at RTL level and implementation of the designed architecture on FPGA technology in a NexysVideo board (Artix 7 FPGA) are done in this work, where the performance, the configurability and the generic of our architecture are highly enhanced. The implementation results indicate that our proposed architectures provide a very high-speed data processing with low needed resources. As an example, with the parameters depth order equal 2, filter order equal 2, order quantization equal 5 and a parallel degree P = 16, we reach a bit rate around 3160 Mega samples per second with low used of logic elements (≈400) and logic registers (≈700).
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Contributor : Fabrice de Almeida Pereira Monteiro <>
Submitted on : Wednesday, July 21, 2021 - 8:05:27 AM
Last modification on : Wednesday, July 21, 2021 - 12:38:02 PM

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Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Safa Saadaoui, Abbas Dandache. Ultra-High Performance and Low-Cost Architecture of Discrete Wavelet Transforms. Wavelet Theory, IntechOpen, 2021, ⟨10.5772/intechopen.94858⟩. ⟨hal-03293395⟩



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