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FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters

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https://hal.univ-lorraine.fr/hal-03293399
Contributor : Fabrice de Almeida Pereira Monteiro <>
Submitted on : Wednesday, July 21, 2021 - 8:19:14 AM
Last modification on : Wednesday, July 21, 2021 - 12:38:11 PM

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Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Juliana Srour, Abbas Dandache. FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters. Advances in Science, Technology and Engineering Systems Journal, Advances in Science Technology and Engineering Systems Journal (ASTESJ), 2018, 3 (5), pp.116-107. ⟨10.25046/aj030516⟩. ⟨hal-03293399⟩

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