FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters - Université de Lorraine Accéder directement au contenu
Article Dans Une Revue Advances in Science, Technology and Engineering Systems Journal Année : 2018

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hal-03293399 , version 1 (21-07-2021)

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Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Juliana Srour, Abbas Dandache. FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters. Advances in Science, Technology and Engineering Systems Journal, 2018, 3 (5), pp.116-107. ⟨10.25046/aj030516⟩. ⟨hal-03293399⟩
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