J. L. Philippe, A. Baganne, and E. Martin, A formal technique for hardware interface design, IEEE Trans. on Circuits And Systems, vol.45, pp.584-591, 1998.

]. M. Aic94 and . Aichouchi, Etude des liens entre la synthèse architecturale et la synthèse au niveau transfert de registres, Thèse de doctorat, 1994.

K. [. Allen and . Kennedy, Optimizing compilers for modern architectures, 2001.

J. T. Pizarro and A. C. Parker, Mlinar : Maha : a program for data path synthesis

J. Armstrong, Making reliable distributed systems in the presence of software errors The Royal Institute of Technology, Thèse de doctorat, 2003.

J. Armstrong, Programming erlang, software for a concurrent world. Pragmatic Programmers, 2007.

]. P. Ba03 and . Brunet, Hardware partitioning software for dynamically reconfigurable soc design, Proc. the 3rd IEEE, 1998.

]. A. Bag97 and . Baganne, Methodologie de synthèse des unités de communication matérielles dans une approche de conception mixte logiciel/matériel (codesign), Thèse de doctorat, 1997.

S. Bouchoux and E. Bourennane, An application based on dynamic reconfiguration of fpgas : Jpeg2000 arithmetic decoder, Optical Engineering, vol.44, 2005.

]. E. Ber97 and . Berrebi, Méthodologie pour l'application industrielle de la synthèse comportementale, Thèse de doctorat, 1997.

P. Bomel, Plate-forme de prototypage rapide fondée sur la synthèse de haut niveau pour applications de radiocommunications, Thèse de doctorat, 2004.

]. N. Bou04 and . Boudouani, Architectures reconfigurables dynamiquement : synthèse matérielle d'opérateurs de détection et d'estimation de mouvement temps réel, Thèse de doctorat, 2004.

A. Beletska-et-pierluigi-san and . Pietro, Extracting coarse-grained parallelism with the affine transformation framework and its limitations, pp.5-20133, 2006.

P. Brunet, Exploration multicritères d'architecturesàarchitecturesà Reconfiguration Dynamique, Thèse de doctorat, 2004.

]. P. Ca01, Chodowiec et al : Fast implementation of secret-key block ciphers using mixed inner-and outer-round pipelining, Proc. of the Symposium on Field Programmable Gate Array -FPGA 2001, pp.94-102, 2001.

M. P. João, Cardoso : On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures, IEEE Trans. ON COMPU- TERS, vol.52, issue.10, 2003.

C. [. Pattanam, D. Dawson, and . Roberts, The verilog procedural interface for the verilog hardware description language, Proc. of IEEE International Verilog HDL Conference, pp.26-28, 1996.

B. Haskell, R. Curry, and . Feys, Haskell 98 language and libraries : The revised report, CG03] P. Chodowiec et K. Gal : Very compact fpga of the aes algorithm Proc. of the workshop on Cryptographic Hardware and Embedded Systems -CHES 2003, pp.319-333, 2002.

]. S. Cha98 and . Chandrasekhar, Partitioning method and algorithms for configurable compution machines, 1998.

J. Cocke, Global common subexpression elimination, Proc. of Symposium on Compiler Construction, pp.850-856, 1970.
DOI : 10.1145/390013.808480

W. [. Camposano and . Wolf, High level VLSI synthesis, 1991.
DOI : 10.1007/978-1-4615-3966-7

M. Paindavoine, S. Weber, and D. Demigny, Architecturè a reconfiguration dynamique pour le traitement temps réel des images. Revue technique et Science de l'information , Numéro Spécial programmation des Architectures Reconfigurables, 1998.

]. N. Dem91 and . Demassieux, Architecture VLSI pour le traitement d'images : une contribution ` a l'´ etude du traitement matériel de l'information, Thèse de doctorat, Ecole nationale supérieure des télécommunications (ENST), 1991.

]. A. Dgl92a, D. Wu, N. Gajski, S. Dutt, and . Lin, High-Level Synthesis, Introduction to chip and system design, 1992.

]. N. Dgl92b, D. Dutt, A. Gajski, S. Wu, and . Lin, High level Synthesis : Introduction to Chip and System Design, 1992.

]. K. Chehida, Partitionnement pour la conception de systèmes réactifsréactifsà flots de données sur architectures reconfigurable, Proc. of SympAAA'2003, 2003.

]. P. Bibliographie-[-ell00 and . Ellervee, High Level Synthesis of Control and Memory Intensive Applications

. [. Philippe and O. Martin, Santieys : Gaut : An architecture synthesis tool for dedicated signal processors, Proc. of IEEE Intl. European Design Automation Conference (Euro DAC'93), pp.14-19, 1993.

]. G. Est00 and . Estrin, Computer network-based scientific collaboration in the energy research community, 1973-1977 :a memoir, IEEE Annals of the History of Computing, vol.22, issue.4

]. G. Est02 and . Estrin, Reconfigurable computer origins : The ucla fixed-plus-variable (f+v) structure computer, IEEE Annals of the History of Computing, vol.24, issue.4, pp.3-9

R. [. Estrin and . Turn, Automatic Assignment of Computations in a Variable Structure Computer System, IEEE Transactions on Electronic Computers, vol.12, issue.6, pp.755-773, 1963.
DOI : 10.1109/PGEC.1963.263559

]. P. Fea92a and . Feautrier, Some efficient solutions to the affine scheduling problem, part i, one dimensional time, International Journal of Parallel Programming, issue.21, pp.313-348, 1992.

]. P. Fea92b and . Feautrier, Some efficient solutions to the affine scheduling problem, part ii, multidimensional time, International Journal of Parallel Programming, issue.21, pp.389-420, 1992.

]. P. Fea94 and . Feautrier, Toward automatic distribution, Journal of Parallel Processing Letters, issue.4, pp.233-244, 1994.

]. J. Fis90, Fishburn : Clock skew optimization, IEEE Trans. On Computers, vol.39, pp.945-951, 1990.

]. A. Gar00 and . Garcia, Etude sur l'estimation et l'optimisation de la consommation de puissance des circuits logiques programmables du type FPGA, Thèse de doctorat, 2000.

E. Senn, G. Corre, N. Julien, and E. Martin, Contraintes mémoire et solution architecturale pour applications tdsi, Proc. of Actes du colloque GRETSI, 2003.

E. Senn, G. Corre, N. Julien, and E. Martin, Ordonnancement sous contraintes de mémorisation : une optimisation efficace des ressources lors de la synthèse d'architecture, Proc. of Actes des Journées Francophones d'Etudes Faible Tension Faible Consommation (FTFC'03), 2003.

D. [. Guccione and . Levi, Design advantages of run-time reconfiguration, Proc

]. S. Gov95 and . Govindarajan, Scheduling algorithms for high level synthesis, 1995.

]. S. Gov00 and . Govindarajan, Algorithms for Design Space Exploration and High Level Synthesis for Multi-FPGA Reconfigurable Computers, Thèse de doctorat, 2000.

]. H. Gue97 and . Guermoud, Architecture reconfigurable dynamiquement dédiées aux traitements en temps réel des signaux vidéo, Thèse de doctorat, 1997.

[. Hara, Function cell optimization in behavioral synthesis, Proc. of the 9th EuroMicro Conference on Digital System Design (DSD'06), 2006.

]. M. Hei96 and . Heijligers, The application of Genetic Algorithms to High-Level Synthesis, Thèse de doctorat, 1996.

[. Tisserand, S. Weber, H. Guermoud, and Y. Berviller, Architecturè a base de fpga reconfigurable dynamiquement dédiée au traitement d'image sur flot de données, Proc. of 16° colloque GRETSI, 1997.

Z. Lin, H. Zhou, and W. Cao, Research on vhdl rtl synthesis system, Proc. the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA.02), 2002.

[. Irisa, Cours master : Optimisations de code indépendantes de l'architecture cible, 2001.

E. Kenneth and . Iverson, A Programming Language, 1962.

[. Diguet, EPICURE: A partitioning and co-design framework for reconfigurable computing, Special issue on FPGA-based Reconfigurable Computing, pp.367-387, 2006.
DOI : 10.1016/j.micpro.2006.02.015

URL : https://hal.archives-ouvertes.fr/hal-00089393

J. P. Diguet, J. L. Philippe, O. Sentieys, and E. Martin, From digital signal processing specification to layout. Logic and Architecture Synthesis : state of-the-art and novel approaches, pp.307-313, 1995.

[. Joan and R. Vincent, A Specification for the AES Algorithm, Dr. Brian Gladman, V3.11, 2003.

M. Karthikeya, Temporal partitioning and scheduling data flow graphs for reconfigurable computers, IEEE Transactions on Computers, vol.48, issue.6, 1999.

T. N. Mudge, K. A. Sakallah, and O. A. , Olukotun : Check tc and min tc : Timing verification and optimal clocking of digital circuits, Proc. of ICCAD'90, pp.552-555, 1990.

]. P. Kis96 and . Kission, Exploitation de la hiérarchie et de la réutilisation de blocs existants par la synthèse de haut niveau, Thèse de doctorat, 1996.

K. [. Bayar, M. Paulsson, J. Hübner, and . Becker, Exploitation of run-time partial reconfiguration for dynamic power management in xilinx spartan iii-based systems

]. K. Kuc98 and . Kuchcinski, An approach to high level synthesis using constraint logic programming, Proc. 24th EUROMICRO '98 Conference on Engineering Systems and Software for the Next Decade, 1998.

M. Kaul and R. Vemuri, Optimal temporal partitioning and synthesis for reconfigurable architectures, Proceedings Design, Automation and Test in Europe, 1998.
DOI : 10.1109/DATE.1998.655887

URL : http://www.ece.uc.edu/~ddel/publications/kaul-date-98.ps

]. Kwny98, K. Zhang, and G. H. Ng, Young : Design representation for dynamically reconfigurable systems, Proc. of the 5th Annual Australasian Conference on Parallel And Real-Time Systems(PART'98), pp.14-23, 1998.

]. P. La00 and . Lakshmikanthan, Behavioural partitioning with synthesis for multi-fpga architectures under interconnect, area, and latency constraints, Proc. 15th IPDPS 2000 Workshops, p.924, 2000.

T. Liu, Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system, 2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006.
DOI : 10.1109/ICECS.2006.379627

J. [. Lysaght and . Dunlop, Dynamic reconfiguration of fpgas, pp.82-94, 1994.

]. Y. Lin97a and . Lin, Recent Development in High Level Synthesis, KNational Science Council of R.O.C, 1997.

L. Yong-loug, Recent developments in high level synthesis, ACM trans, Design Automation of Electronic systems, vol.2, issue.1, pp.2-21, 1997.

]. T. Liu04 and . Liu, Implantation d'un algorithme de cryptage en reconfiguration dynamique et synthèse architecturale, 2004.

L. [. Abel and D. Kessal, Demigny : Real-time image processing using dynamic reconfiguration paradigm : architecture and programming, 2006.

L. [. Kaviani, K. Shang, and . Bathala, Dynamic power consumption in virtexii fpga family, Proc. of International Symposium on Field-Programmable Gate Arrays, pp.157-164, 2002.

]. Y. Ma05 and . Moullec, Design trotter : System-level dynamic estimation task a 1st step towards platform architecture selection, Journal of embedded computing, vol.4, issue.4, 2005.

[. Mtibaa, An Iterative Method for Algorithms Implementation on a Limited Dynamically Reconfigurable Hardware, Journal of Computer Science, vol.2, issue.5, pp.422-430, 2006.
DOI : 10.3844/jcssp.2006.422.430

J. P. Diguet, . A. Fornari, . C. Fouilliart, . G. Gamrat, . P. Gogniat et al., Partitionning and codesign tolls and methodology for reconfigurable computing : the epicure philosophy, Proc. of the Third International Workshop on Systems, 2003.

M. Mcloone and J. Mccanny, High performance single chip fpga rijdael algorithm implementation, Proc. of Proceedings of the Workshop on Cryptographic Hardware and Embedded systems-CHES 2001, pp.65-76, 2001.

M. [. Parker, R. Mcfarland, and . Camposani, The high-level synthesis of digital systems, Proc. of the IEEE, pp.301-318, 1990.

. [. Micallef-trigona, Datapath intensive asic design-synthesis from vhdl

]. S. Muc97 and . Muchnick, Advanced Compiler Design and Implementation, 1997.

]. M. Nar98 and . Narasimhan, Exact scheduling techniques for high level synthesis, Master of Science in Electrical Engineering, 1998.

X. [. Ng and . Zhang, Module allocation for dynamically reconfigurable systems

]. I. Oa98 and . Ouaiss, An integrated partitioning and synthesis system for dynamically reconfigurable multi-fpga architectures, Proc. of Fifth Reconfigurable Architectures Workshop (RAW'98), pp.31-36, 1998.

A. D. , P. Boulet, and G. Andr-silber, Loop parallelization algorithms : from parallelism extraction to code generation, 1997.
DOI : 10.1016/s0167-8191(98)00020-9

URL : https://hal.archives-ouvertes.fr/inria-00565000

J. [. Paulin and . Knight, Force-directed scheduling in automatic data path synthesis, 24th ACM/IEEE conference proceedings on Design automation conference , DAC '87, pp.195-202, 1987.
DOI : 10.1145/37888.37918

]. K. Poo02 and . Poon, Power estimation for field programmable gate arrays, 2002.

J. [. Pramstaller and . Worlerstorfer, A Universal and Efficient AES Coprocessor for Field Programmable Logic Arrays, FPL 2004, pp.565-574, 2004.
DOI : 10.1007/978-3-540-30117-2_58

M. Karabernou, R. Bourguiba, D. Demigny, and L. Kessal, Designing a new architecture for real time image analysis with dynamically configurable fpgas, Proc. of IEEE IMACS Computational Engineering in Systems Applications, 1998.

R. [. Pillement, D. David, and . Chillet, Sentieys : Dart : a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints, Proc. of In Parallel and Distributed Processing Symposium (IPDPS02), pp.156-163, 2002.

G. Sassatelli, Highly scalable dynamically reconfigurable systolic ringarchitecture for dsp applications, Proc. of Design, Automation and Test in Europe Conference and Exhibition (DATE02), pp.553-558, 2002.
DOI : 10.1109/date.2002.998355

M. S. Kishinevsky, . N. Rotem, . N. Savoiu, . R. Dutt, S. Gupta et al., Nicolau : Coordinated transformations for high-level synthesis of high performance microprocessor blocks, Proc. of Design Automation Conference, 2002.

R. Gupta, S. Gupta, N. Dutt, and A. Nicolau, Coordinated parallelizing compiler optimizations and high-level synthesis, ACM Transactions on Design Automation of Electronic Systems, vol.9, issue.4, 2002.
DOI : 10.1145/1027084.1027087

URL : http://www.cecs.uci.edu/technical_report/TR02-35.pdf

R. Gupta, S. Gupta, N. Dutt, and A. Nicolau, Loop shifting and compaction for the high-level synthesis of designs with complex control flow, Proceedings Design, Automation and Test in Europe Conference and Exhibition
DOI : 10.1109/DATE.2004.1268836

]. J. Sil94 and . Silc, Scheduling strategies in high level synthesis, Jozef Stefan Institute, vol.52, 1994.

R. [. Sharma and . Jain, Estimating architectural resources and performance for high-level synthesis applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, issue.2, pp.175-190, 1993.
DOI : 10.1109/92.238417

H. [. Catthoor, S. De-man, W. Note, and . Guerts, Cathedral-iii : Architecturedriven high-level synthesis for high throughput dsp applications, Proc. of 28th ACM/IEEE Design Automation Conference, 1991.

]. Ste97 and . Steven, Advanced Compiler Design and Implementation, pp.378-396, 1997.

]. N. Ta00 and . Togawa, synopsys.com/products/logic/dc-ultra-ds.pdf Automated design synthesis and partitioning for adaptive reconfigurable hardware, Proc. Of the ASP-DAC, pp.309-312, 2000.

]. C. Ta03 and . Tanougast, Temporal partitioning methodology optimizing fpga resources for dynamically reconfigurable embedded real-time system, Microprocessors and Microsystems, vol.27, issue.3, pp.115-130, 2003.

. Bibliographie and . Tanougast, Méthodologie de partitionnement applicable aux systèmes sur pucè a base de FPGA, pour l'implantation en reconfiguration dynamique d'algorithmes flot de données, Thèse de doctorat, 2001.

J. R. Hauser, T. J. Callahan, and J. Wawrzynek, The garp architecture and c compiler, IEEE Trans. Comp, vol.3, issue.4, pp.62-69, 2000.

T. [. Yang and . Friedman, Methods used in automatic design generator (alert)

]. J. Tho04 and . Thorvinger, Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support, Thèse de doctorat, 2004.

J. Veitch, A History and Description of CLOS. Handbook of Programming Languages, Volume IV : Functional and Logic Programming Languages, pp.107-158, 1998.

]. R. Vem01 and . Vemuri, Automated design synthesis and partitioning for adaptive reconfigurable hardware. Hardware implementation of intelligent systems, Physica-Verlag GmbH, 2001.

J. Willoughby, Synthesis support for design partitiong, the IEEE International Verilog HDL Conference (IVC'97, 1997.

]. M. Wir97, Wirthlin : Improving Functional Density Through Run-Time Circuit Reconfiguration, Thèse de doctorat, 1997.

W. [. Lam and . Lim, Communication-free parallelization via affine transformations
DOI : 10.1007/BFb0025873

W. [. Lam and . Lim, Maximizing parallelism and minimizing synchronization with affine transforms, Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages , POPL '97, 1997.
DOI : 10.1145/263699.263719

K. W. Ng-xue-jie and G. Zhang, Young : High-level synthesis using genetic algorithms for dynamically reconfigurable fpgas, Proc. of the 23rd Euromicro Conference (EUROMICRO' 97, 1997.

]. G. Zim79 and . Zimmermann, The mimola design system : A computer aided digital processor design method, Proc. of the Design Automation Conference, 1979.

]. X. Zn00a, K. Zhang, and . Ng, Module allocation for dynamically reconfigurable systems, Proc. 15th IPDPS 2000 Workshops, p.932, 2000.

]. Zn00b, K. Zhang, and . Ng, An effective high-level synthesis approach for dynamically reconfigurable systems, Proc. of the 4th International/Conference Exhibition on High Performance Computing in Asia-Pacific Region, 2000.