E. Annexe, A. Liste-des-publications-@bullet-mohsin, R. Abbas, M. Fabrice, D. Camille et al., A Self-Checking HW Journal for a Fault Tolerant Processor Architecture, International Journal of Reconfigurable Computing, issue.11, 2011.

@. Mohsin, A. Abbas, R. Fabrice, M. Camille, D. Abbas et al., A Dependable Stack Processor Core for MPSoC Development, XXIV Conference on Design of Circuits and Integrated Systems (DCIS'09), 2009.

@. Mohsin, A. Fabrice, M. Camille, D. Abbas, R. Abbas et al., A HW/SW Mixed Mechanism to Improve the Dependability of a Stack Processor, 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS'09), 2009.

@. Mohsin, A. Camille, D. Fabrice, M. Abbas, R. Abbas et al., Journalized Stack Processor for Reliable Embedded Systems, 1st International Conference on Aerospace Science and Engineering (ICASE'09), 2009.

@. A. Ramazani, M. Amin, F. Monteiro, C. Diou, and A. Dandache, A fault tolerant journalized stack processor architecture, 2009 15th IEEE International On-Line Testing Symposium, pp.24-27, 2009.
DOI : 10.1109/IOLTS.2009.5196013

@. Mohsin, A. Camille, D. Fabrice, M. Abbas, R. Abbas et al., Error Detecting and Correcting Journal for Dependable Processor Core, GDR System on Chip -System in Package (GDR-SoC-SiP'10), pp.9-11, 2010.

C. @bullet-mohsin-amin, F. Diou, A. Monteiro, and . Ramazani, Design Methodology of Reliable Stack Processor Core, GDR System on Chip -System in Package, 2009.

A. @bullet-mohsin, Self-Organization in Embedded Systems, 2nd Winter School on Self Organization in Embedded Systems, Schloss Dagstuhl, 2007.

V. Dans-le, Erreur(s) dans l'UVJ (b) erreur(s), p.109

]. J. Bibliographie-[-acc-+-93, A. Arlat, Y. Costes, J. Crouzet, D. Laprie et al., Fault injection and dependability evaluation of fault-tolerant systems, IEEE Transactions on Computers, pp.913-923, 1993.

. Aeroflex, Dual-Core LEON3FT SPARC v8 processor, 2011.

P. [. Aidemark, J. Folkesson, and . Karlsson, A Framework for Node-Level Fault Tolerance in Distributed Real-Time Systems, 2005 International Conference on Dependable Systems and Networks (DSN'05), pp.656-665, 2005.
DOI : 10.1109/DSN.2005.7

C. [. Amgalan, S. Hachmann, H. J. Hellebrand, and . Wunderlich, Signature Rollback - A Technique for Testing Robust Circuits, 26th IEEE VLSI Test Symposium (vts 2008), pp.125-130, 2008.
DOI : 10.1109/VTS.2008.34

R. H. Ando, Y. Kan, K. Tosaka, K. Takahisa, and . Hatanaka, Validation of hardware error recovery mechanisms for the SPARC64 v microprocessor, Dependable Systems and Networks With FTCS and DCC IEEE International Conference on, pp.62-69, 2008.

J. [. Avizienis, B. Laprie, and . Randell, Fundamental concepts of dependability, 2001.

F. M. Amin, C. Monteiro, A. Diou, A. Ramazani, and . Dandache, A HW/SW mixed mechanism to improve the dependability of a stack processor, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2009), pp.976-979, 2009.
DOI : 10.1109/ICECS.2009.5410845

[. Arm, Cortex-R4 and Cortex-R4F. Technical reference manual, 2009.

A. Amin and . Ramazani, A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture, International Journal of Reconfigurable Computing, vol.15, issue.1-2
DOI : 10.1109/2.386985

[. Bailey, Comparison of GreenArrays chips with texas instruments MSP430F5xx as micropower controllers, 2010.

]. R. Bau05 and . Baumann, Radiation-induced soft errors in advanced semiconductor technologies, BIBLIOGRAPHIE IEEE Transactions on Device and materials reliability, vol.5, issue.3, pp.305-316, 2005.

]. D. Bbv-+-05, B. Bernick, P. Bruckert, D. Vigna, R. Garcia et al., NonStop advanced architecture, Proceedings of International Conference on Dependable Systems and Networks, 2005 (DSN'05), pp.12-21, 2005.

C. [. Bridgford, C. W. Carmichael, and . Tseng, Single-event upset mitigation selection guide, Xilinx Application Note, vol.987, 2008.

]. J. Bgb-+-08, J. Baraza, S. Gracia, D. Blanc, P. Gil et al., Enhancement of fault injection techniques based on the modification of VHDL code, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.693-706, 2008.

]. R. Bic10 and . Bickham, An Analysis of Error Detection Techniques for Arithmetic Logic Units, 2010.

D. [. Bowen and . Pradhan, Virtual checkpoints : Architecture and performance. Computers, IEEE Transactions on, vol.41, issue.5, pp.516-525, 2002.
DOI : 10.1109/12.142677

P. [. Briere and . Traverse, AIRBUS A320/A330/A340 electrical flight controls - A family of fault-tolerant systems, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing, pp.616-623, 1993.
DOI : 10.1109/FTCS.1993.627364

]. C. Car01 and . Carmichael, Triple module redundancy design techniques for virtex FPGAs, Xilinx Application Note XAPP197, vol.1, 2001.

]. L. Che08 and . Chen, Hsiao-Code check matrices and recursively balanced matrices. Arxiv preprint, 2008.

[. Chang, E. A. Ha, and . Lee, Heterogeneous simulation -mixing Discrete-Event models with dataflow Fault injection : A method for validating computer-system dependability, The Journal of VLSI Signal Processing, vol.15, issue.1/2, pp.127-144, 1997.
DOI : 10.1023/A:1007930622942

S. K. Constantinides, J. Plaza, B. Blome, V. Zhang, S. Bertacco et al., BulletProof: A Defect~Tolerant CMP Switch Architecture, The Twelfth International Symposium on High-Performance Computer Architecture, 2006., pp.5-16, 2006.
DOI : 10.1109/HPCA.2006.1598108

URL : http://cccp.eecs.umich.edu/papers/kypros-hpca06.pdf

. L. Cts-+-10-]-c, N. N. Chen, A. J. Tendolkar, M. Y. Sutton, D. C. Hsiao et al., Faulttolerance design of the IBM enterprise system/9000 type 9021 processors, IBM Journal of Research and Development, vol.36, issue.4, pp.765-779, 2010.

E. N. Elnozahy, L. Alvisi, Y. Wang, and D. Johnson, A survey of rollback-recovery protocols in message-passing systems, ACM Computing Surveys, vol.34, issue.3, pp.375-408, 2002.
DOI : 10.1145/568522.568525

D. Ernst, N. Kim, S. Das, S. Pant, R. Rao et al., Razor: a low-power pipeline based on circuit-level timing speculation, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), pp.7-18, 2003.
DOI : 10.1109/MICRO.2003.1253179

K. [. Forsati, F. Faez, A. Moradi, and . Rahbar, A Fault Tolerant Method for Residue Arithmetic Circuits, 2009 International Conference on Information Management and Engineering, pp.59-63, 2009.
DOI : 10.1109/ICIME.2009.111

R. Fernández-pascual, J. Garcia, M. Acacio, and J. Duato, Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level, IEEE Transactions on Parallel and Distributed Systems, vol.21, issue.8, pp.1117-1131, 2010.
DOI : 10.1109/TPDS.2009.148

S. [. Feng, A. Gupta, S. Ansari, and . Mahlke, Shoestring, ACM SIGPLAN Notices, vol.45, issue.3, pp.385-396, 2010.
DOI : 10.1145/1735971.1736063

D. [. Fujiwara and . Pradhan, Error-control coding in computers, Computer, vol.23, issue.7, pp.63-72, 2002.
DOI : 10.1109/2.56853

S. [. Ghosh, N. Basu, . [. Touba, E. Gaisler, and . Catovic, Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits, Proceedings of Data Systems in Aerospace, pp.63-72, 2005.
DOI : 10.1166/jolpe.2005.007

]. S. Gha11 and . Ghaznavi, Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA, 2011.

R. [. Grottke, K. Matias, and . Trivedi, The fundamentals of software aging, 2008 IEEE International Conference on Software Reliability Engineering Workshops (ISSRE Wksp), pp.1-6, 2008.
DOI : 10.1109/ISSREW.2008.5355512

V. [. Godlewski, D. Pouget, M. Lewis, and . Lisart, Electrical modeling of the effect of beam profile for pulsed laser fault injection, Microelectronics Reliability, vol.49, issue.9-11, pp.9-111143, 2009.
DOI : 10.1016/j.microrel.2009.07.037

URL : https://hal.archives-ouvertes.fr/hal-00669736

]. J. Hay05 and . Hayes, The architecture of the scalable configurable instrument processor, 2005.

M. Y. Hsiao, W. Carter, J. Thomas, and W. Stringfellow, Reliability, Availability, and Serviceability of IBM Computer Systems: A Quarter Century of Progress, IBM Journal of Research and Development, vol.25, issue.5, pp.453-468, 2010.
DOI : 10.1147/rd.255.0453

J. [. Harris and . Hayes, Functional programming on a Stack-Based embedded processor, 2006.

]. M. Hsi10 and . Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM Journal of Research and Development, vol.14, issue.4, pp.395-401, 2010.

Z. [. Iyer and . Kalbarczyk, Hardware and software error detection, 2003.

. Jaber, Conception architecturale haut débit et sûre de fonctionnement pour les codes correcteurs d'erreurs Méthodologie de conception d'architectures de processeur sûres de fonctionnement pour les applications mécatroniques, 2009.

M. Jallouli, C. Diou, F. Monteiro, and A. Dandache, Stack processor architecture and development methods suitable for dependable applications, Reconfigurable Communication-centric SoCs (ReCoSoC'07), 2007.

. [. Jesd89a, Measurement and reporting of alpha particle and terrestrial cosmic ray-induced soft errors in semiconductor devices, 2006.

W. J. Johnson, M. Howes, D. Wirthlin, M. Mcmurtrey, P. Caffrey et al., Using Duplication with Compare for On-line Error Detection in FPGA-based Designs, 2008 IEEE Aerospace Conference, pp.1-11, 2008.
DOI : 10.1109/AERO.2008.4526470

[. Jr, Stack computers : the new wave, 1989.

C. [. Koren, I. Krishna, and . Books24x7, Fault-tolerant systems, 2007.

. Kks-+-07-]-p, J. Kudva, P. Kellington, R. Sanda, J. Mcbeth et al., Fault injection verification of IBM POWER6 soft error resilience, Architectural Support for Gigascale Integration (ASGI) Workshop, 2007.

J. W. Kellington, R. Mcbeth, P. Sanda, and R. Kalla, IBM POWER6 processor soft error tolerance analysis using proton irradiation, Proceedings of the IEEE Workshop on Silicon Errors in Logic?Systems Effects (SELSE) Conference, 2009.

]. H. Kop04 and . Kopetz, From a federated to an integrated architecture for dependable embedded systems, 2004.

]. H. Kop11 and . Kopetz, Real-time systems : design principles for distributed embedded applications, 2011.

]. P. Lal05 and . Lala, Single error correction and double error detecting coding scheme, Laprie. Sûreté de fonctionnement des systèmes : concepts de base et terminologie, 2004.

J. [. Li, J. G. Armstrong, and . Tront, An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow, IEEE Transactions on Nuclear Science, vol.31, issue.6, pp.311139-1144, 2007.
DOI : 10.1109/TNS.1984.4333471

R. [. Laprie and . Brian, Origins and integration of the concepts, 2007.

]. I. Lbs-+-11, M. Lee, M. Basoglu, D. Sullivan, L. Yoon et al., Survey of error and fault detection mechanisms, 2011.

L. [. Lisboa and . Carro, XOR-Based Low Cost Checkers for Combinational Logic, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.281-289, 2008.
DOI : 10.1109/DFT.2008.35

[. Lee and J. Na, A Novel Simulation Fault Injection Method for Dependability Analysis, IEEE Design & Test of Computers, vol.26, issue.6, pp.50-61, 2009.
DOI : 10.1109/MDT.2009.135

[. Laprie, B. Randell, and C. Landwehr, Basic concepts and taxonomy of dependable and secure computing, IEEE Trans. on Dependable Secure Computers, vol.1, issue.1, pp.11-33, 2004.

R. [. Madan and . Balasubramonian, Power Efficient Approaches to Redundant Multithreading, IEEE Transactions on Parallel and Distributed Systems, vol.18, issue.8, pp.1066-1079, 2007.
DOI : 10.1109/TPDS.2007.1090

M. [. Meixner, D. Bauer, and . Sorin, Argus : Low-cost, comprehensive error detection in simple cores, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp.210-222, 2007.

A. [. Maloney and . Goscinski, A survey and review of the current state of rollback-recovery for cluster systems, Concurrency and Computation: Practice and Experience, vol.40, issue.4, pp.1632-1666, 2009.
DOI : 10.1109/TSE.1975.6312842

[. Mitra and E. J. Mccluskey, Which concurrent error detection scheme to choose ?, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000.
DOI : 10.1109/TEST.2000.894311

K. Morgan, D. Mcmurtrey, B. Pratt, and M. J. Wirthlin, A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs, IEEE Transactions on Nuclear Science, vol.54, issue.6, pp.2065-2072, 2007.
DOI : 10.1109/TNS.2007.910871

N. [. Macwilliams and . Sloane, The theory of error-correcting codes, 2006.

D. [. Meixner and . Sorin, Error Detection Using Dynamic Dataflow Verification, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), pp.104-118, 2007.
DOI : 10.1109/PACT.2007.4336204

URL : http://www.ee.duke.edu/~sorin/papers/pact07_ddfv.pdf

M. J. Mack, W. M. Sauer, S. B. Swaney, and B. G. Mealey, IBM POWER6 reliability, IBM Journal of Research and Development, vol.51, issue.6, pp.763-774, 2010.
DOI : 10.1147/rd.516.0763

]. S. Muk08 and . Mukherjee, Architecture design for soft errors, 2008.

E. [. Mastipuram and . Wee, Soft errors' impact on system reliability, EDN, 2004.

M. [. May and . Woods, A New Physical Mechanism for Soft Errors in Dynamic Memories, 16th International Reliability Physics Symposium, pp.33-40, 2007.
DOI : 10.1109/IRPS.1978.362815

T. Naughton, W. Bland, G. Vallee, C. Engelmann, and S. Scott, Fault injection framework for system resilience evaluation, Proceedings of the 2009 workshop on Resiliency in high performance, Resilience '09, pp.23-28, 2002.
DOI : 10.1145/1552526.1552530

J. Nakano, P. Montesinos, K. Gharachorloo, and J. Torrellas, ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers, The Twelfth International Symposium on High-Performance Computer Architecture, 2006., pp.200-211, 2006.
DOI : 10.1109/HPCA.2006.1598129

M. Nicolaidis, K. Torki, F. Natali, F. Belhaddad, and D. Alexandrescu, Implementation and validation of a low-cost single-event latchup mitigation scheme, IEEE Workshop on Silicon Errors in Logic?System Effects (SELSE), 2009.
URL : https://hal.archives-ouvertes.fr/hal-01413151

Y. [. Narayanan and . Xie, Reliability concerns in embedded system designs, Computer, vol.39, issue.1, pp.118-120, 2006.
DOI : 10.1109/MC.2006.31

A. Patel, Fault tolerant features of modern processors, 2010.

[. Pelc and C. Bailey, Ubiquitous forth objects, Euro-forth'04, 2004.

L. [. Patel and . Fung, Concurrent Error Detection in ALU's by Recomputing with Shifted Operands, IEEE Transactions on Computers, vol.31, issue.7, pp.589-595, 2006.
DOI : 10.1109/TC.1982.1676055

]. S. Pie06 and . Piestrak, Dependable computing : Problems, techniques and their applications, First Winter School on Self-Organization in Embedded Systems, Schloss Dagstuhl, 2006.

V. [. Pop, P. Izosimov, Z. Eles, and . Peng, Design optimization of time-and costconstrained fault-tolerant embedded systems with checkpointing and replication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.389-402, 2005.

]. D. Pow10 and . Powell, A generic fault-tolerant architecture for real-time dependable systems, 2010.

H. Quinn, P. Graham, J. Krone, M. Caffrey, and S. Rezgui, Radiation-induced multi-bit upsets in SRAM-based FPGAs, IEEE Transactions on Nuclear Science, vol.52, issue.6, pp.2455-2461, 2006.
DOI : 10.1109/TNS.2005.860742

S. [. Qin, Y. Lu, and . Zhou, SafeMem : exploiting ECC-memory for detecting memory leaks and memory corruption during production runs, 11th International Symposium on High-Performance Computer Architecture, pp.291-302, 2005.

M. A. Ramazani, F. Amin, C. Monteiro, A. Diou, and . Dandache, A fault tolerant journalized stack processor architecture, 2009 15th IEEE International On-Line Testing Symposium, 2009.
DOI : 10.1109/IOLTS.2009.5196013

I. [. Reis, Software modulated fault tolerance, 2008.

P. [. Rivers and . Kudva, Reliability Challenges and System Performance at the Architecture Level, IEEE Design & Test of Computers, vol.26, issue.6, pp.62-73, 2009.
DOI : 10.1109/MDT.2009.153

U. K. Rothbart, C. Neffe, R. Steger, E. Weiss, A. Rieger et al., A smart card test environment using multi-level fault injection in SystemC, Proceedings of 6th IEEE Latin-American Test Workshop 2005, pp.103-108, 2005.

E. [. Reddy and . Rotenberg, Coverage of a microarchitecture-level fault check regimen in a superscalar processor, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN), pp.1-10, 2008.
DOI : 10.1109/DSN.2008.4630065

M. Rebaudengo, S. Reorda, M. Torchiano, and M. Violante, Soft-error detection through software fault-tolerance techniques, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), pp.210-218, 2002.
DOI : 10.1109/DFTVS.1999.802887

A. [. Rahbaran and . Steininger, Is Asynchronous Logic More Robust Than Synchronous Logic?, IEEE Transactions on Dependable and Secure Computing, vol.6, issue.4, pp.282-294, 2009.
DOI : 10.1109/TDSC.2008.37

W. Rao, C. Yang, R. Karri, and A. Orailoglu, Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge, Computer, vol.44, issue.2, pp.46-53, 2011.
DOI : 10.1109/MC.2011.1

M. Schoeberl, A Java processor architecture for embedded real-time systems, Journal of Systems Architecture, vol.54, issue.1-2, 2008.
DOI : 10.1016/j.sysarc.2007.06.001

URL : http://www.jopdesign.com/doc/rtarch.pdf

J. [. Srinivasan, W. H. Farquharson, B. L. Robinson, and . Bhuva, Evaluation of error detection strategies for an FPGA-Based Self-Checking arithmetic and logic unit, MAPLD International Conference, 2005.

T. [. Spainhower and . Gregg, IBM S/390 Parallel Enterprise Server G5 fault tolerance: A historical perspective, IBM Journal of Research and Development, vol.43, issue.5.6, pp.863-873, 2010.
DOI : 10.1147/rd.435.0863

[. Shannon, A C Compiler for Stack Machines, 2006.

. Shlr-+-09-]-s, M. Sastry-hari, P. Li, B. Ramachandran, S. Choi et al., mSWAT : lowcost hardware fault detection and diagnosis for multicore systems, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp.122-132, 2009.

D. J. Sorin, M. M. Martin, M. Hill, and D. Wood, SafetyNet, Proceedings of the 29th annual international symposium on Computer architecture, pp.123-134, 2002.
DOI : 10.1145/545214.545229

]. A. Smr-+-07, T. Shye, V. J. Moseley, J. Reddi, D. A. Blomstedt et al., Using processlevel redundancy to exploit multiple cores for transient fault tolerance, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, pp.297-306, 2007.

]. D. Sor09 and . Sorin, Fault tolerant computer architecture, 2009.

]. J. Ssf-+-08, M. Schwank, D. Shaneyfelt, J. Fleetwood, P. Felix et al., Radiation effects in MOS oxides, IEEE Transactions on Nuclear Science, vol.55, issue.4, pp.1833-1853, 2008.

W. Stallings, Computer Organization and Architecture, 2006.

C. [. Ting and . Moore, Mup21 a high performance misc processor. Forth Dimensions, 1995.

]. C. Too11 and . Toomey, Statical Fault Injection and Analysis at the Register Transfer Level using the Verilog Procedural Interface, 2011.

]. V. Van08, A. Vanhauwaert, M. Vahdatpour, S. Fazeli, and . Miremadi, Fault injection based dependability analysis in a FPGA-based enviroment Transient error detection in embedded systems using reconfigurable components, International Symposium on Industrial Embedded Systems, pp.1-6, 2006.

V. [. Vayrynen, E. Singh, and . Larsson, Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.484-489, 2009.
DOI : 10.1109/DATE.2009.5090713

URL : http://liu.diva-portal.org/smash/get/diva2:286358/FULLTEXT01

V. [. Wang, Single Event Upset: An Embedded Tutorial, 21st International Conference on VLSI Design (VLSID 2008), pp.429-434, 2008.
DOI : 10.1109/VLSI.2008.28

URL : http://www.eng.auburn.edu/~vagrawal/TALKS/wang-singleeventupset.pdf

K. [. Wells, G. Chakraborty, and . Sohi, Adapting to intermittent faults in multicore systems, ACM SIGPLAN Notices, vol.43, issue.3, pp.255-264, 2008.
DOI : 10.1145/1353536.1346314

URL : https://minds.wisconsin.edu/bitstream/handle/1793/60576/TR1605.pdf?sequence=1

J. [. Webb and . Liptay, A high-frequency custom CMOS s/390 microprocessor
DOI : 10.1109/iccd.1997.628874

]. Y. Yeh02 and . Yeh, Triple-triple redundant 777 primary flight computer, 1996 IEEE Aerospace Applications Conference. Proceedings, pp.293-307, 2002.
DOI : 10.1109/AERO.1996.495891

J. [. Zhang and . Jiang, Bibliographical review on reconfigurable fault-tolerant control systems, Annual Reviews in Control, vol.32, issue.2, pp.229-252, 2008.
DOI : 10.1016/j.arcontrol.2008.03.008

J. F. Ziegler and W. A. Lanford, The effect of sea level cosmic rays on electronic devices