Auxiliary Dedicated Module) dans un processeur modulaire et hautement parallèle développé au LICM []. Les ADM de ce processeur, basé sur un caeur de DSp, sont dédiés à I'exécution de fonctions critiques. Dans ce cas présent, la fonction critique est le codage canal, pp.202-203 ,
<< Etude et développement d'un nouvelle architecture de processeur DSP dédiée aux applications modem en télécommunication sur câble T.V r>, Déc, 1999. ,
Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1, Proceedings of ICC '93, IEEE International Conference on Communications, pp.64-1070, 1993. ,
DOI : 10.1109/ICC.1993.397441
< Les turbo codes parallèles et séries, décodage SISO et performance ML )), rapport, 1998. ,
Iterative detection and decoding for wireless communication )), manuscrit de thèse PhD, 1999. ,
Serial concatenation of interleaved codes: performance analysis, design, and iterative decoding, IEEE Transactions on Information Theory, vol.44, issue.3, pp.909-926, 1998. ,
DOI : 10.1109/18.669119
< Transfer function bounds on the performance of hubo codes >>, 1995. ,
Fondements de la Théorie de la Transmission de L'Information, 1987. ,
Sciences et Avenir, hors-série, pp.28-29, 1999. ,
Error Control Coding: Fundamentals and Applications, 1983. ,
Théorie de l'Information ou Analyse Diacritique des systèmes, BIBLIOGRAPHIE, 1986. ,
< Contribution à la conception de circuits et de systèmes pour les applications télécom >, Travaux Scientifiques en Vue d'une Habilitation à Diriger des Recherches, 2000. ,
Itoh, < Viterbi decoding algorithm for convolutional codes with repeat request >>, IEEE Trans. on Inf Theory, issue.5, p.26, 1980. ,
DOI : 10.1109/tit.1980.1056245
URL : http://hirosuke.it.k.u-tokyo.ac.jp/pdfs/IT-80-540.pdf
A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001. ,
DOI : 10.1109/ICECS.2001.957437
< Parallel encoder and decoder architectures for cyclic codes >, IEIEC Trans. on Fundamentals, vol.879, pp.3-3, 1996. ,
< Study of a new parallel architecture dedicated to the family of the difference set cyclic codes >>, Proc. 5th IEEE Int. On-Line Testing Worl<shop, pp.237-239, 1999. ,
< Panallel CRC computation in FPGA's >>, Proc. 6th Int. lV'orlaehop on Field- Programmable Logic: Smart Applications, New Paradigms and Compilers, pp.156-165, 1996. ,
High-speed parallel CRC circuits in VLSI, IEEE Transactions on Communications, vol.40, issue.4, pp.653-657, 1992. ,
DOI : 10.1109/26.141415
High-speed error correction circuit based on iterative cells, International Journal of Electronics, vol.74, issue.4, pp.529-540, 1993. ,
DOI : 10.1109/40.60527
< 50 MHz CMOS pipelined majority logic decoder for (1057,813) difference-set cyclic code >, IEICE Trans, vol.79, pp.60-067, 1996. ,
<< Fast configurable polynomial division for error control coding applications >>, Proc., IOLTW 2001, pp.158-161, 2001. ,
Introduction aux codes correcteurs, Edition Marketing, 1990. ,
Data Compression and Error Control Techniques with Applications, p.985 ,
< Error bounds for convolutional codes and an asymptotically optimum decoding algorithm >, IEEE Trans. on Inf, pp.260-269, 1967. ,
The application of error control to communications, IEEE Communications Magazine, vol.25, issue.4, pp.44-57 ,
DOI : 10.1109/MCOM.1987.1093590
< Overview of existing and projected uses of coding in military satellite communications >, NTC Conf, 1977. ,
< Alternate symbol inversion for improved symbol synchronisation in convolutionally coded system >>, IEEE Trans. Commun.,COM, p.28, 1980. ,
< Electronique spatiale: Les Nouveaux défis dus aux ceintures de radiation >>, Rewe de l'électricité et de l'électronique, pp.54-62, 1999. ,
Satellites free the mobile phone, IEEE Spectrum, vol.35, issue.3, pp.26-35, 1998. ,
DOI : 10.1109/6.663755
< On improving data link performance by increasing the channel alphabet and introducing sequence coding >>, IEEE Int. Symp. on Inf. Theory, 1976. ,
Channel coding with multilevel/phase signals, IEEE Transactions on Information Theory, vol.28, issue.1, pp.55-67, 1982. ,
DOI : 10.1109/TIT.1982.1056454
< A novel coded modulation scheme employing turbo codes D, 1995. ,
DOI : 10.1049/el:19951064
< On the design of nubo codes >, pp.99-121, 1995. ,
An introduction to turbo codes >, Bradley Dept. of Elect. Eng. Virginia Polytechnic Inst. S. U ,
Research activities on UMTS radio interface, network architectures, and planning, IEEE Communications Magazine, vol.36, issue.2, 1998. ,
DOI : 10.1109/35.648769
The 2nd, Int. Symp. on Turbo Codes, pp.535-538, 2000. ,
<< DSP implementation of turbo decoders for satellite communications >>, 6th Int. Workshop on Digital Signal Processing Techniques for Space Applications, 1998. ,
< An infoduction to INMARSAT's new mobile multimedia serrtice >>,6th Int. Mobile Satellite Conf, pp.226-229, 1999. ,
Research elements leading to the development of INMARSAT's new mobile multimedia services >>,6th Int, pp.209-212, 1999. ,
< Multimedia services for aeronautical mobile satellite applications >>, 6th Int, Mobile Satellite Conf, pp.1-4, 1999. ,
< Turbo codec -QPSK modem for INTELSAT digital services >>, The 2nd Int, Symp. on Turbo Codes, pp.487-490, 2000. ,
s deep-space telecommunications road map >>,JPL TMO Progress Report 42'136 gen : Performance evaluation of proposed TTCM (PCCC) with R-S code and without R-S code >>, TIEI, 1999. ,
< Proposal on using multi-tone turbo trellis coded modulation >, TIEI.4 fNapa, California), 2000. ,
< Turbo codes for PR4 and EPR4 magnetic recording >, The 32nd Asilomar Conf, on Signals, Systems and Computers, pp.1778-1782, 1998. ,
< Performance of high rate turbo codes on a PR4-equalized magnetic recording channel >, Int, Conf. on Commun, pp.947-951, 1998. ,
Error Control Coding handbook, Linkabit Corporation, 1976. ,
DOI : 10.21236/ada156195
URL : http://www.dtic.mil/dtic/tr/fulltext/u2/a156195.pdf
The subtleties and intricacies of building a constraint lenght l5 convolutional decoder >, Applications of error control coding >>, pp.1810-1819253, 1992. ,
Utilisation des turbo codes pour un système de communication multimédia par satellite >, Thèse ENST Toulouse, 1999. ,
Design of parallel concatenated convolutional codes, IEEE Transactions on Communications, vol.44, issue.5, pp.591-600, 1996. ,
DOI : 10.1109/26.494303
< Weight distributions for turbo codes using random and nonrandom permutations >>, 1995. ,
< On the design of concatenated coding systemi with interlea vers >>, TMO progress report 4 2-I 3 4, 0998. ,
Combined MMSE interference suppression and turbo coding for a coherent DS-CDMA system, IEEE Journal on Selected Areas in Communications, vol.19, issue.9, pp.1793-1803, 2001. ,
DOI : 10.1109/49.947043
URL : http://vivaldi.ucsd.edu:8080/starpapers/./Tang-jsac01_2.pdf
< Turbo codes for PR4: Parallel versus serial concatenation >>, Proc. IEEE Int. Conf, on Commun., Paper S4l-4, 1999. ,
< Unveiling turbo codes: Some results on parallel concatenated coding schemes >>, IEEE Trans. on Inf, Theory, vol.42, issue.2, pp.409-428, 1996. ,
Role of recursive convolutional codes in turbo codes, Electronics Letters, vol.31, issue.11, pp.858-859, 1995. ,
DOI : 10.1049/el:19950622
Application of distance spectrum analysis to the improvement of turbo code performance >>, Proc. 35th Annual Allerton Conf, on Commun., Control, and Computing, pp.701-710, 1997. ,
< Multiple turbo codes for deep-space communication >>, 1995. ,
DOI : 10.1109/isit.1995.531137
< Optimal inaerleaving scheme for convolutional codes >>, Elecronics Letters, vol.25, issue.22, 0989. ,
< Interleaver design for turbo codes with selected inputs > ,
< Convolutional interleavers for stream-oriented parallel concatenated convolutional codes >>,ISIT, 1998. ,
< Interleaving techniques for coded modulation for mobile communications >>, Centerfor lVîreless Commun. Report, p.207 ,
<< Turbo code termination scheme and a novel altemative for short frames >>, Proc. IEEE PIMRC, pp.354-358, 1996. ,
DOI : 10.1109/pimrc.1996.567415
URL : http://web.rsise.anu.edu.au/~mreed/papers/PIMRC96.ps.gz
Terminating the trellis of turbo-codes in the same state, Electronics Letters, vol.31, issue.1, pp.22-23, 1995. ,
DOI : 10.1049/el:19950008
Turbo code termination and interleaver conditions, Electronics Letters, vol.31, issue.24, pp.2082-2083, 1995. ,
DOI : 10.1049/el:19951410
Interleaver design for turbo codes, Electronics Letters, vol.30, issue.25, pp.2107-2108, 1994. ,
DOI : 10.1049/el:19941434
An IC for turbo-codes encoding and decoding >>, Proc. IEEE Int. Solid-State Circuits Conf, pp.90-91, 1995. ,
<< Rate compatible turbo codes >> Electronics Letters, pp.535-536, 1995. ,
DOI : 10.1049/el:19950406
< Soft-output decoding algorithms in iterative decoding ofturbo codes >, TDA Progress, 1996. ,
DOI : 10.1002/ett.4460090206
URL : http://porto.polito.it/1663995/1/ett_siso_2.pdf
< A comparison of optimal and sub-optimal decoding algorithms in the log domain >>, Proc.,fCC, pp.1009-1013, 1995. ,
Improved decoding with the SOVA in a parallel concatenated (Turbo-code) scheme, Proceedings of ICC/SUPERCOMM '96, International Conference on Communications, pp.102-106, 1996. ,
DOI : 10.1109/ICC.1996.540253
Optimal decoding of linear codes for minimizing symbol error rate (Corresp.), IEEE Transactions on Information Theory, vol.20, issue.2, pp.284-287, 1974. ,
DOI : 10.1109/TIT.1974.1055186
< High-speed VLSI architectures for soft-output viterbi decoding >, Proc. Application Specific Array Processors, pp.373-384, 1992. ,
Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding, Proceedings of 6th International Symposium on Personal, Indoor and Mobile Radio Communications, pp.193-197, 1995. ,
DOI : 10.1109/PIMRC.1995.476882
Implementation of high throughput soft output Viterbi decoders, IEEE Workshop on Signal Processing Systems, pp.146-151 ,
DOI : 10.1109/SIPS.2002.1049700
A 40 Mb/s soft-output Viterbi decoder, IEEE Journal of Solid-State Circuits, vol.30, issue.7, pp.812-830, 1995. ,
DOI : 10.1109/4.391121
High-speed parallel Viterbi decoding: algorithm and VLSI-architecture, IEEE Communications Magazine, vol.29, issue.5, pp.46-55, 1991. ,
DOI : 10.1109/35.79382
A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder, Proceedings ISSCC '95, International Solid-State Circuits Conference, pp.88-92140, 1995. ,
DOI : 10.1109/ISSCC.1995.535288
A 1-Gb/s, four-state, sliding block Viterbi decoder, IEEE Journal of Solid-State Circuits, vol.32, issue.6, pp.7-97, 0997. ,
DOI : 10.1109/4.585246
URL : http://my.com.nthu.edu.tw/~jmwu/LAB/Sliding-Blk-Viterbi-Meng.pdf
Reduced-complexity viterbi detector architectures for partial response signaling >>, Proc. IEEE GLOBECOM, pp.559-563, 1995. ,
DOI : 10.1109/glocom.1995.501991
Sontag, < A New Architecure For the Fast Viterbi Algorithm >>, Proc. IEEE GLOBECOM, pp.1664-1668, 2000. ,
A 140 Mbits/s, 32 state, radix-4 viterbi decoder >>, IEEE J. of Solid-State Circuits, vol.27, issue.l2, 1992. ,
DOI : 10.1109/isscc.1992.200415
Prodcut specifrcation AHA450I astro 36 Mbits/sec turbo code encoder/decoder >,Specification Product, I 998 ,
Satellite systems geax up to meet the challenges of global networks >. Disponible sur htç, 2002. ,
16 compatible turbo product code decoder vl.l >>, Product Specification D5212, 2003. ,
<< Performance of a low-complexity turbo decoder with a simple early stopping criterion implemented on a SHARC processor >>, 6th Int, pp.28-286, 1999. ,
< Why systolic architectures? >>, Computer 15, I, pp.37-46, 1982. ,
DOI : 10.1109/mc.1982.1653825
URL : http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=kung_-_1982_-_why_systolic_architectures.pdf
< Special purpose device for signal and image processing: An opportunity in VLSI >>, Proc. ,SP/E, Real Time and Signal Processing III, 1980. ,
< An efficient systolic array for the l-D convolution problem >>, J. of VLSI Computer Systems, pp.398-407, 1986. ,
A high speed encoder for recursive systematic convolutive codes )), 8th IEEE Int, Line Testing Worlaehop, 2002. ,
Intoduction To Parallel Algorithms and Architectures, 1992. ,