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Conference Papers Year : 2024

A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving

Abstract

We present a novel technique for Electrical Rule Checking (ERC) based on formal methods. We define a relational semantics of Integrated Circuits (IC) as a means to model circuits’ behavior at transistor-level. We use Z3, a Satisfiability Modulo Theory (SMT) solver, to verify electrical properties on circuits — thanks to the defined semantics. We demonstrate the usability of the approach to detect current leakage due to missing level-shifter on large industrial circuits, and we conduct experiments to study the scalability of the approach.
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Dates and versions

hal-04527225 , version 1 (29-03-2024)

Identifiers

  • HAL Id : hal-04527225 , version 1

Cite

Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, et al.. A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. Design, Automation and Test in Europe Conference, Mar 2024, Valencia, Spain. ⟨hal-04527225⟩
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