TRACES is a Research group on Architectures and Compilers for Embedded Systems.

Our research contributes to the verification of critical computer systems that must meet strong timing requirements. The key point of such a verification is the computation of upper bounds on execution and response times.

These last years, we have focused on the modeling of hardware platforms and application software to determine safe and as-tight-as-possible Worst-Case Execution Times (WCET). The approaches that we have proposed are mainly based on static code analysis techniques. Our results have been integrated in the open-source OTAWA toolset, which has been used in various academic and industrial projects, as well as by other research groups.

We currently consider three topics:

• analysis and control of timing interferences in multi-core platforms
• coupling (hardware/software) analyses to improve the accuracy of timing estimations
• timing analysis of emerging applications, such as neural networks.