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Modélisation des effets de la reconfiguration dynamique sur la flexibilité d'une architecture de traitement temps réel

Abstract : The principal contribution of the wired logic compared to the microprocessor is the degree of parallelism which is in higher several orders of magnitude. However, the property of configurability of these circuits involves an additionnal cost in term of silicon surface, delay and power consumption compared to circuits ASICs. The dynamic reconfiguration of the FPGA is often presented in the literature like a means of increasing their flexibility, to approach that of the microprocessors, while preserving a level of performance that if not is close to the ASIC is higher than of the microprocessors. If the performance is in general, for a given application, more easy to quantify, the situation is quite different for flexibility. In the litterature this metric has never been defined and quantified. Moreover we did not find any definition of the flexibility of an architecture for processing of data. The principal objective of this work is by one hand, to define and quantify the flexibility and by the other hand, to model the influence of the dynamic reconfiguration on flexibility. We put at the disposition the designer a metric as well as the bases of methodology allowing it to choose or not this solution according to its constraints and objectives.
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Theses
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http://docnum.univ-lorraine.fr/prive/SCD_T_2007_0139_PEREZ_CASTANEDA.pdf
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https://hal.univ-lorraine.fr/tel-01748171
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Submitted on : Thursday, March 29, 2018 - 11:27:11 AM
Last modification on : Tuesday, March 10, 2020 - 10:52:09 AM

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  • HAL Id : tel-01748171, version 1

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Oscar Leopoldo Perez Castañeda. Modélisation des effets de la reconfiguration dynamique sur la flexibilité d'une architecture de traitement temps réel. Autre. Université Henri Poincaré - Nancy 1, 2007. Français. ⟨NNT : 2007NAN10139⟩. ⟨tel-01748171⟩

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