Optimisation par synthèse architecturale des méthodes de partitionnement temporel pour les circuits reconfigurables

Abstract : aThe research work presented in the context of methodologies is to assist the implementation of data flow graph algorithms on dynamically reconfigurable RSoC (Reconfigurable System on Chip)-based FPGA architectures.The main strategy consists in implementing a design approach based on simultaneously both the dynamic reconfiguration (DR) and synthesis architecture (SA) in order to achieve a best Adequacy Algorithm Architecture (A3). The methodology consists in identifying and extracting the parts of an application which is described in form of DFG in order to implement either by successively partial reconfiguration (TP), or by the AS or by combining the two approaches.To develop our solution with a view of optimizing and suitable compromise between the two approaches RD and SA, we propose a parameter in order to evaluate the degree of the inter-partition implementation based on functional units shared. In order to validate the proposed methodological strategy, we present the results of the implementation of our approach on two real-time applications. A comparative analysis with the respecting of the implementation results illustrates the interest and the optimisation ability of our method, which is also for dynamic reconfiguration implementation of the complex applications on RSoC.
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Ting Liu. Optimisation par synthèse architecturale des méthodes de partitionnement temporel pour les circuits reconfigurables. Autre [cs.OH]. Université Henri Poincaré - Nancy 1, 2008. Français. ⟨NNT : 2008NAN10013⟩. ⟨tel-01748325⟩

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