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Implantation paramétrable d'un nouvel algorithme de cryptage symétrique basé Chaos par inclusion au sein d'une architecture reconfigurable de type FPGA

Abstract : Since 1980, the idea of using dynamic systems with chaotic behaviour for the design of encryption/decryption algorithms has attracted increasing: attention from researchers. The strong dynamics of chaotic systems such as sensitivity to initial conditions and control parameters, the unpredictability in the long term and broad-spectrum can provide important properties such as confusion and diffusion usually meet in standard cryptography. In addition, there are two possible approaches for designing chaos-based cryptosystems: analog and digital. Analog encryption techniques are primarily based on chaos-synchronization, while the chaotic digital encryption approaches do not depend on the chaos-synchronization and can be implemented either in software or hardware. This thesis focuses on the digital design and implementation of a new cryptosystem based on chaos-synchronization. The discovery of the possibility of chaos synchronization in 1990 opens the door to investigation digital chaos-based encryption. Indeed, many contributions are made for many promising achievements of digital cryptosystems. However, a number of recently proposed digital chaotic ciphers have been shown that they are not secure enough and they are cryptanalyzed. In addition, in order to design more secure digital chaotic ciphers and meet the security requirements in embedded systems, rules and new mechanisms must be carefully considered to make up the flaws in the design flow. However, the problem of the degradation dynamics of chaotic systems has not been seriously considered by most designers of digital chaotic ciphers. Furthermore, most all the digital chaos-based cryptosystems proposed in the literature does not address the issue of real-time embedded applications. Consequently, the tasks of these thesis works focus on the design solutions providing the real secure suitable for embedded applications. Our contributions in this thesis are, firstly the design and hardware implementation on reconfigurable FPGA technology of a pseudo-random key generator based on chaotic systems (continuous and discrete). Secondly, the statistical analysis detailed security of the proposed generators. Thirdly, the development, the conception and the integration of a new chaotic generator in a symmetric stream cipher, includes the resolution problem of the chaos synchronization between the transmitter (encryption) and receiver (decryption). Fourthly, the hardware implementation of the proposed cryptosystem on real encryption applications. i.e. the encryption/decryption of real-time audio, image and video data. In addition, a performance evaluation and comparisons with previous conventional and chaos-based ciphers is performed in order to extract these weaknesses and strengths and define future work prospects
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http://docnum.univ-lorraine.fr/prive/DDOC_T_2012_0385_AZZAZ.pdf
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Mohamed Salah Azzaz. Implantation paramétrable d'un nouvel algorithme de cryptage symétrique basé Chaos par inclusion au sein d'une architecture reconfigurable de type FPGA. Autre. Université de Lorraine, 2012. Français. ⟨NNT : 2012LORR0385⟩. ⟨tel-01749595⟩

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