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Étude d'une architecture parallèle de processeur pour la transmission de données à haut débit

Abstract : The work presented here is part of a general project within the LICM laboratory, concerning the architectural design of a high data rate transmission system. The main objective is to design a specialized processor for fast processing of the lower layer protocols in the reference models (OSI, Internet, ITU-T/ATM). The technology evolution and increasing of the bandwidth of the physical transmission media have transferred the bottleneck concerning the available data rates of the communication networks towards the network active node equipments. Managing the protocol diversity, the data heterogeneity, and high data rates requires a substantial improvement of the processing power in these equipments. Although this problem has been largely addressed concerning routers and switches, end-user equipments (e.g : modems and network interface cards) are still far from matching the requirement of high data rates. The design of a specialized processor architecture depends strongly on the characteristics of applications to which the processor is dedicated. The architecture selected for the processor is a set of interconnected general processing units (mini processor cores) or specialized modules (auxiliary modules). The goal is to offer a high level of parallel processing capacity. The development of such an architecture requires a suitable design methodology to be defined, which starts by a study of representative network protocols. First of all, the goal is to identify among the principal tasks (operations of the protocols) the most common and the most critical. The critical tasks (from the realtime point of view) are processed by specialized modules (whose study is not our goal). The remaining tasks are performed by the general processing units, whose study is the main subject of this work. Potential performance of these general units is evaluated for various target architectures (CISC, RISC, superscalair, VLIW). The time performance evaluation of architectures is based on the algorithm modelling using Markov chains which was used to implement the simulation tools. In order not to favour a particular architecture, we introduced a virtual processor model to encode the algorithms without introducing any constrains related to actual architectures. The analysis of the simulation results allowed us to find good architectures/algorithms adequacy. The performance of the overall processor architecture (parallel operation of the processing units) was evaluated under various traffic conditions. A simplified interconnection model (compared to the final model) was used which allowed to connect the processing units in a pseudo-pipeline (linear or not) chain. Lastly, two types of general processing units (mini processor cores) have been designed in VHDL at the RTL level and validated on FPGA.
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Abbas Ramazani. Étude d'une architecture parallèle de processeur pour la transmission de données à haut débit. Autre [cs.OH]. Université Paul Verlaine - Metz, 2005. Français. ⟨NNT : 2005METZ006S⟩. ⟨tel-01752436⟩

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