Skip to Main content Skip to Navigation
Theses

Conception architecturale haut débit et sûre de fonctionnement pour les codes correcteurs d'erreurs

Abstract : Nowadays, modern communication systems require higher and higher data throughputs to transmit increasing volumes of data. They must be flexible to handle multi-norms environments, and progressive to accommodate future norms. For these systems, quality of service (QoS) must be guaranteed despite the evolution of microelectronics technologies that increase the sensitivity of integrated circuits to external perturbations (impact of particles, loss of signal integrity, etc). Fault-tolerance techniques are becoming more and more an important criteria to improve the dependability and the quality of service. This thesis?work continues previous research undertaken at the LICM laboratory on the architectural design of high-speed, low-cost, and dependable transmission systems. It focuses on two principal areas of research : The first research area concerns the speed and flexibility aspects, particularly on the study and implementation of parallel-pipelined architectures dedicated to recursive convolutional encoders. The principle is based on the optimization of blocks that calculate the remainder of the polynomial division which constitute the critical operation of the encoding. This approach is generalized to recursive IIR filters. The main architectural characteristics being aimed are high flexibility and scalability, yet preserving a good trade-off between the amount of resources used (and hence, area consumption) and the obtained performance (operation speed). The second topic concerns the developing of a methodology for designing FS (fault-secure) encoders, improving the tolerance of digital integrated circuits. The proposed approach consists in adding an extra blocks to the encoders, allowing online error detection. The proposed solutions offer a good compromise between complexity and frequency operation. For even higher throughput, parallel-pipelined implementations of FS encoders were considered. Different fault injection campaigns of single, double, and random errors were applied to the encoders in order to evaluate error detection rates. The study of dependable architecture was extended to pipeline-parallel decoders for cyclic block codes. This approach is based on a slight modification of the parallel-pipeline architectures developed at LICM laboratory, introducing some redundancy in order to make it dependable
Document type :
Theses
Complete list of metadata

Cited literature [177 references]  Display  Hide  Download

https://hal.univ-lorraine.fr/tel-01752666
Contributor : Thèses Ul <>
Submitted on : Thursday, March 29, 2018 - 1:53:55 PM
Last modification on : Monday, April 16, 2018 - 10:42:37 AM

File

Jaber.Houssein.SMZ0942.pdf
Files produced by the author(s)

Identifiers

  • HAL Id : tel-01752666, version 1

Collections

Citation

Houssein Jaber. Conception architecturale haut débit et sûre de fonctionnement pour les codes correcteurs d'erreurs. Autre. Université Paul Verlaine - Metz, 2009. Français. ⟨NNT : 2009METZ042S⟩. ⟨tel-01752666⟩

Share

Metrics

Record views

53

Files downloads

136