In this paper, we propose a robust and compact design architecture of hardware chaotic key generator for real-time images encryption. The new proposed approach combines the perturbation technique with a non-linear switching between multiple three-dimensional continuous chaotic systems. The originality of this new scheme is that it allows a low-cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. This pipelined architecture is particularly attractive since it provides a high security. Numerical simulations and real-time experimental results using Xilinx FPGA Virtex technology have demonstrated the feasibility and the efficiency of our secure solution and can be applied to many secure real-time embedded applications in System on Chip (SoC). Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and key analysis attacks.