A multiprocessor architecture for fast packet processing

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https://hal.univ-lorraine.fr/hal-01883138
Contributor : Camille Diou <>
Submitted on : Thursday, September 27, 2018 - 5:07:46 PM
Last modification on : Saturday, September 29, 2018 - 1:09:53 AM

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A. Ramazani, F. Monteiro, Camille Diou, A. Dandache. A multiprocessor architecture for fast packet processing. 2005 12th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2005), Dec 2005, Gammarth, France. ⟨10.1109/ICECS.2005.4633380⟩. ⟨hal-01883138⟩

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