A multiprocessor architecture for fast packet processing - Université de Lorraine Access content directly
Conference Papers Year : 2005
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hal-01883138 , version 1 (27-09-2018)

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A. Ramazani, F. Monteiro, Camille Diou, A. Dandache. A multiprocessor architecture for fast packet processing. 2005 12th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2005), Dec 2005, Gammarth, France. ⟨10.1109/ICECS.2005.4633380⟩. ⟨hal-01883138⟩

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