A multiprocessor architecture for fast packet processing - Université de Lorraine
Conference Papers Year : 2005

A multiprocessor architecture for fast packet processing

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Electronics Distributed, Parallel, and Cluster Computing [cs.DC] Embedded Systems Hardware Architecture [cs.AR] Micro and nanotechnologies/Microelectronics

Camille Diou  : Connect in order to contact the contributor

https://hal.univ-lorraine.fr/hal-01883138

Submitted on : Thursday, September 27, 2018-5:07:46 PM

Last modification on : Monday, May 24, 2021-5:48:02 PM

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hal-01883138 , version 1 (27-09-2018)

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A. Ramazani, F. Monteiro, Camille Diou, A. Dandache. A multiprocessor architecture for fast packet processing. 2005 12th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2005), Dec 2005, Gammarth, France. ⟨10.1109/ICECS.2005.4633380⟩. ⟨hal-01883138⟩

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