A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation - Université de Lorraine Access content directly
Conference Papers Year : 2019
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hal-03293396 , version 1 (21-07-2021)

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Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Abbas Dandache. A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation. TECHNOLOGIES AND MATERIALS FOR RENEWABLE ENERGY, ENVIRONMENT AND SUSTAINABILITY: TMREES19Gr, Sep 2019, Athens, Greece. pp.020090, ⟨10.1063/1.5138576⟩. ⟨hal-03293396⟩
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