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A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation

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https://hal.univ-lorraine.fr/hal-03293396
Contributor : Fabrice de Almeida Pereira Monteiro <>
Submitted on : Wednesday, July 21, 2021 - 8:12:05 AM
Last modification on : Wednesday, July 21, 2021 - 12:38:03 PM

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Mouhamad Chehaitly, Mohamed Tabaa, Fabrice Monteiro, Abbas Dandache. A generic, configurable and efficient architecture for first and second generation discrete wavelet packet transform with ultra-high speed and low-cost FPGA implementation. TECHNOLOGIES AND MATERIALS FOR RENEWABLE ENERGY, ENVIRONMENT AND SUSTAINABILITY: TMREES19Gr, 2019, Athens, France. pp.020090, ⟨10.1063/1.5138576⟩. ⟨hal-03293396⟩

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