A new FPGA-based DPLL algorithm to improve SAT solvers - Université de Lorraine
Conference Papers Year : 2015

A new FPGA-based DPLL algorithm to improve SAT solvers

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Electronics Hardware Architecture [cs.AR] Embedded Systems Signal and Image processing Engineering Sciences [physics]

Fabrice DE ALMEIDA PEREIRA MONTEIRO  : Connect in order to contact the contributor

https://hal.univ-lorraine.fr/hal-03293452

Submitted on : Wednesday, July 21, 2021-9:23:35 AM

Last modification on : Monday, September 25, 2023-12:28:09 PM

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hal-03293452 , version 1 (21-07-2021)

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Khadija Bousmar, Fabrice Monteiro, Zineb Habbas, Sofiene Dellagi, Abbas Dandache. A new FPGA-based DPLL algorithm to improve SAT solvers. 2015 27th International Conference on Microelectronics (ICM), Dec 2015, Casablanca, France. pp.287-290, ⟨10.1109/ICM.2015.7438045⟩. ⟨hal-03293452⟩

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