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Conference papers

FPGA-based hardware in the loop validation for fault tolerant three-phase active filter

Abstract : This paper proposes a new robust fast power switch fault detection and compensation for a three phase shunt active filter without redundant leg. The approach introduced in this paper minimizes the time interval between the fault occurrences and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 mus by using simultaneously a ldquotime criterionrdquo and a ldquovoltage criterionrdquo without false fault detection due to power semiconductors switching. In order to attain this short detection time a FPGA (field programmable gate array) is used. After fault detection, the classical three-leg shunt active filter is reconfigured in a two-leg topology. In this case the faulty phase is connected to the middle point of the DC bus. The studied fault detection method is implemented using a FPGA and experimentally validated. The experimental results based on ldquoFPGA in the looprdquo hardware prototyping show good agreement with theoretically analyses.
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Conference papers
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https://hal.univ-lorraine.fr/hal-03565790
Contributor : Philippe Poure Connect in order to contact the contributor
Submitted on : Friday, February 11, 2022 - 11:05:20 AM
Last modification on : Monday, March 21, 2022 - 8:47:41 AM

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Shahram Karimi, Shahrokh Saadate, Philippe Poure. FPGA-based hardware in the loop validation for fault tolerant three-phase active filter. 2008 IEEE International Symposium on Industrial Electronics (ISIE 2008), Jun 2008, Cambridge, United Kingdom. pp.2189-2194, ⟨10.1109/ISIE.2008.4676980⟩. ⟨hal-03565790⟩

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