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A fault tolerant three-leg shunt active filter using FPGA for fast switch failure detection

Abstract : The reliability of the VSI (Voltage Source Inverter) components such as semi-conductor switches is critical for the shunt active power filters. A failure in one of the switches decreases system performances and usually leads to disconnect the filter. So, to prevent such undesirable events, real-time fault detection, isolation and compensation must be implemented. This paper proposes new robust fast power switch fault detection and compensation for a three phase shunt active filter without redundant leg. The approach introduced in this paper minimizes the time interval between the fault occurrence in the semi-conductor switches, used in VSI, and its diagnosis. This paper demonstrates that a faulty switch can be detected in less than 10 mus without false fault detection due to power semiconductors switching by using simultaneously a "time criterion" and a "voltage criterion". To attain this short detection time, a FPGA (Field Programmable Gate Array) implementation is mandatory. After fault detection, the classical three-leg shunt active filter is reconfigured in a two-leg topology. In this case the faulty phase is connected to the middle point of the DC bus. The experimental results based on "FPGA in the loop" hardware prototyping validate the performances of the proposed fault detection method for the reconfigurable three-leg active filter topology.
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https://hal.univ-lorraine.fr/hal-03565812
Contributor : Philippe Poure Connect in order to contact the contributor
Submitted on : Friday, February 11, 2022 - 11:14:41 AM
Last modification on : Monday, March 21, 2022 - 8:47:41 AM

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Shahram Karimi, Philippe Poure, Shahrokh Saadate. A fault tolerant three-leg shunt active filter using FPGA for fast switch failure detection. 2008 IEEE Power Electronics Specialists Conference - PESC 2008, Jun 2008, Rhodes, Greece. pp.3342-3347, ⟨10.1109/PESC.2008.4592471⟩. ⟨hal-03565812⟩

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