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Design of power electronic digital controller based on FPGA/SOC using VHDL-AMS language

Abstract

In this paper, authors detail a Top-down design methodology for Power Electronic digital controller based on Field Programmable Gate Aray or System-On-Chip. This design flow uses VHDL-AMS language. The application case of a shunt three phase power active filter is studied. An optimised architecture is designed and each step is detailed. Each block of the architecture is modeled in VHDL at several abstraction levels, from real data format to specific binary format. To achieve closed loop simulation, analog and power elements are modeled in VHDL-AMS. The whole closed loop system is successfully validated at various abstraction levels of the digital control, using ADVanceMS.
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Dates and versions

hal-03565834 , version 1 (11-02-2022)

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Slavisa Jovanovic, Philippe Poure. Design of power electronic digital controller based on FPGA/SOC using VHDL-AMS language. 2007 IEEE International Symposium on Industrial Electronics, Jun 2007, Vigo, Spain. pp.2301-2306, ⟨10.1109/ISIE.2007.4374966⟩. ⟨hal-03565834⟩
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