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Méthodologie de partitionnement applicable aux systèmes sur puce à base de FPGA, pour l'implantation en reconfiguration dynamique d'algorithmes flot de données

Abstract : The Run-Time Reconfiguration of FPGAs consist in the successive execution of a sequence of algorithms on the same device. In this thesis, we discuss the partitioning problem for dynamic reprogramability. We propose a method for the determination of the step numbers for a Run-Time-Reconfiguration implementation of a given time-constrained algorithm. This permits to enhance the silicon efficiency by reducing the reconfigurable array's area. Our method consist, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. This evaluation helps us to find a final partitioning. This method can be made in a heuristic way to adapt more precisely the partitioning. To validate our methodology, we have applied our approach on real time image processing algorithms. The performances like processing time and resources usage rate of the FPGA are described. Finally we conclude with suggestions for further work.
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Theses
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http://docnum.univ-lorraine.fr/prive/SCD_T_2001_0169_TANOUGAST.pdf
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https://hal.univ-lorraine.fr/tel-01746560
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Submitted on : Thursday, March 29, 2018 - 10:40:19 AM
Last modification on : Monday, December 14, 2020 - 3:01:34 PM

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  • HAL Id : tel-01746560, version 1

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Camel Tanougast. Méthodologie de partitionnement applicable aux systèmes sur puce à base de FPGA, pour l'implantation en reconfiguration dynamique d'algorithmes flot de données. Autre. Université Henri Poincaré - Nancy 1, 2001. Français. ⟨NNT : 2001NAN10169⟩. ⟨tel-01746560⟩

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