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Conception d'une architecture journalisée tolérante aux fautes pour un processeur à pile de données

Abstract : In this thesis, we propose a new approach to designing a fault tolerant processor. The methodology is addressing several goals including high level of protection against transient faults along with reasonable performance and area overhead trade-offs. The resulting fault-tolerant processor will be used as a building block in a fault tolerant MPSoC (Multi-Processor System-on-Chip) architecture. The concepts being used to achieve fault tolerance are based on concurrent detection and rollback error recovery techniques. The core elements in this architecture are a stack processor core from the MISC (Minimal Instruction Set Computer) class and a hardware journal in charge of preventing error propagation to the main memory (supposedly dependable) and limiting the impact of the rollback mechanism on time performance. The design methodology relies on modeling at different abstraction levels and simulating modes, developing dedicated software tools, and prototyping on FPGA technology. The results, obtained without seeking a thorough optimization, show clearly the relevance of the proposed approach, offering a good compromise in terms of protection and performance. Indeed, fault tolerance, as revealed by several error injection campaigns, prove to be high with 100% of errors being detected and recovered for single bit error patterns, and about 60% and 78% for double and triple bit error patterns, respectively. Furthermore, recovery rate is still acceptable for larger error patterns, with yet a recovery rate of 36%on 8 bit error patterns
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Submitted on : Thursday, March 29, 2018 - 11:59:24 AM
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  • HAL Id : tel-01749037, version 1



Mohsin Amin. Conception d'une architecture journalisée tolérante aux fautes pour un processeur à pile de données. Autre. Université Paul Verlaine - Metz, 2011. Français. ⟨NNT : 2011METZ017S⟩. ⟨tel-01749037⟩



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