Méthodologie de conception d'architectures de processeur sûres de fonctionnement pour les applications mécatroniques

Abstract : Nowadays, embedded systems are becoming increasingly attractive for many applications. Furthermore, these systems should be more and more dependable. Indeed, systems such as mechatronic or automatically controlled ones often work in harsh environmental conditions making them more prone to errors due to disturbances. Thus, designers should consider ways to protect them against such errors. In this work, a special interest is dedicated to processor architecture dependability as we consider processor-based systems. The stack computer philosophy has been chosen for the processor architecture in order to achieve a good trade-off between simplicity and effectiveness. Our approach to introduce and evaluate the dependability is based on the development and the use of a software emulator of the processor to be designed. Dependability of the processor is ensured through the collaborative use of hardware and software protection techniques: hardware error detection means and software error correction means. The correction technique is implemented in benchmarks and is validated on the emulator through a simulation of various scenarios of errors appearance. Different parameters are evaluated such as correction capability and time overhead. This correction technique is independent from the target application and from the detection means, what confirms the methodological aspect of our approach. Otherwise, as requested by the CIM?tronic project, we integrated our work with the CRAN Nancy/A3SI Metz one by applying the information flow approach on the processor instruction set. We showed the ability of this approach to evaluate the whole processor/application dependability
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Mehdi Jallouli. Méthodologie de conception d'architectures de processeur sûres de fonctionnement pour les applications mécatroniques. Autre. Université Paul Verlaine - Metz, 2009. Français. ⟨NNT : 2009METZ006S⟩. ⟨tel-01752621⟩

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