In this paper, a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a working frequency of 200MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.