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Architectures numériques configurables pour le traitement rapide sur FPGA de codes correcteurs d’erreurs de la famille QC-LDPC

Abstract : Wireless connectivity has turned essential in a growing number of systems in nearly all the domains of activity, either professional or personal. The concerned applications and devices, very varied, must make use of ever increasing and changing protocols. This constantly incurs new constraints and requirements that can only be faced with permanent innovation effort in the fields of transmission techniques, hardware/software architectures and design methodologies. The reliable transmission of data at high data rates over noisy and hence unreliable channels, requires channel coding to be used most of the time employing error correcting codes. Of these, LDPC codes are among the most effective concerning their ability to achieve near Shannon limit performance. This makes them very attractive in many areas and standars (eg. DVB-S2 in digital television, IEEE 802.11n [WiFi] and IEEE 802.16e [WiMAX] in wireless networks). The work in this thesis proposes a new architectures that is fast and easily configurable for the coding and decoding of codes from the QC-LDPC sub-family of LDPC codes. The proposed encoder and decoder architectures target implementation on FPGA. These architectures provide processing speeds that can be very high thanks to highly parallel hardware structures. Configurable parameters relate to the target code characteristics and the desired degree of parallel processing. The proposed architectures have been validated for many QC-LDPC codes. Each time, different levels of parallel processing were selected to vary the trade-off between performance (processing speed, id. flow) and cost (hardware area requirements). Despite the constraints inherent to the choice of configurability, rather high flow rates can be achieved with reasonable level of parallelism. By limiting the level of parallelism, it is possible to greatly restrict the hardware costs without yet too much limiting the achieved throughputs.
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Alaa Aldin Al Hariri. Architectures numériques configurables pour le traitement rapide sur FPGA de codes correcteurs d’erreurs de la famille QC-LDPC. Sciences de l'ingénieur [physics]. Université de Lorraine, 2015. Français. ⟨NNT : 2015LORR0354⟩. ⟨tel-02526625⟩

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