Service interruption on Monday 11 July from 12:30 to 13:00: all the sites of the CCSD (HAL, EpiSciences, SciencesConf, AureHAL) will be inaccessible (network hardware connection).
Skip to Main content Skip to Navigation
Book section

A Scalable Flexible SOM NoC-based Hardware Architecture

Abstract : In this paper, a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a working frequency of 200MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.
Complete list of metadata

Cited literature [12 references]  Display  Hide  Download
Contributor : Serge Weber Connect in order to contact the contributor
Submitted on : Tuesday, March 12, 2019 - 8:13:39 PM
Last modification on : Monday, December 13, 2021 - 1:52:05 PM
Long-term archiving on: : Thursday, June 13, 2019 - 4:21:40 PM


Files produced by the author(s)




Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui. A Scalable Flexible SOM NoC-based Hardware Architecture. Advances in Self-Organizing Maps and Learning Vector Quantization, pp.165-175, 2016, ⟨10.1007/978-3-319-28518-4_14⟩. ⟨hal-02065672⟩



Record views


Files downloads