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Book Section Year : 2016

A Scalable Flexible SOM NoC-based Hardware Architecture


In this paper, a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a working frequency of 200MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.
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Dates and versions

hal-02065672 , version 1 (12-03-2019)



Mehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui. A Scalable Flexible SOM NoC-based Hardware Architecture. Advances in Self-Organizing Maps and Learning Vector Quantization, pp.165-175, 2016, ⟨10.1007/978-3-319-28518-4_14⟩. ⟨hal-02065672⟩
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